To improve the reliability of random access memories, such as dynamic random access memories (DRAMs), memories may include additional circuitry to correct for single bit failures. The additional circuitry typically implements an error correction code (ECC), such as a Hamming code, where parity bits are generated during memory writes and stored with data bits in the memory. The parity bits are stored in an additional memory area dedicated to storing parity bits. This additional parity memory is not directly accessible by an end user; rather it is used as part of the overall error detection and correction.
ECC calculates parity information and can determine if a bit has switched to an incorrect value. ECC can compare the parity originally calculated to the tested parity and make any corrections to correct for incorrect data values. In some cases, it is desirable to have ECC built directly into a memory chip to provide greater memory chip reliability or to optimize other memory chip properties such as self refresh currents on low power DRAMs. ECC circuitry, however, is typically associated with a large overhead due to additional memory elements used to store the parity information. Typical ECC implementations may cost up to 50% of the memory chip area.
With error correction enabled, single bit failures corrected by the ECC circuitry are invisible to the end user since the memory device provides error free data to the end user. Knowing the number of single bit failures occurring in the background, however, is important for predicting the quality of the overall memory system and for understanding the contribution of the ECC circuitry on the overall memory quality and reliability. A typical memory tester cannot count the “invisible” corrected single bit failures unless the error correction of the memory is disabled, which allows the single bit failures to become visible.
Thus to test a typical memory, the memory is first read with the error correction disabled so that the number of single bit failures can be counted. The memory is then reread with the error correction enabled to test whether the single bit failures are corrected. Therefore for a complete test of the memory, the memory is read twice, which increases test time by more than a factor of two when compared to a non-error correcting memory of the same size. The test time is increased by more than a factor of two since the parity memory is typically treated as an additional separate memory that is tested by reading with the error correction disabled.
For these and other reasons, there is a need for the present invention.